This invention relates to analog-to-digital (hereinafter referred to as A/D) converters and, more particularly, to a parallel comparison type A/D converter using a voltage divider.
A parallel comparison type A/D converter has a construction, in which an analog input voltage V.sub.s is applied to 2.sup.N comparators to which different output voltages from a voltage divider dividing a reference voltage V.sub.R are supplied as respective reference voltages, the results of comparison of the input voltage with the reference voltages in the comparators being encoded to produce a digital output, and it is disclosed in, for instance, Andrew G. F. Dingwall, "Monolithic Expandable 6 Bit CMOS/SOS A/D Converter", ISSCC Digest of Technical Paper, PP. 126-127, 1979.
FIG. 1 shows an example of the parallel comparison type A/D converter, in which N=3. Numeral N represents the number of bits of the digital output of the A/D converter. The A/D converter comprises a voltage divider 10 which includes a plurality of resistors 12 to 19 connected in series. Junctions of adjacent resistors constitute respective output terminals 20 to 27. The voltage divider 10 is connected between a reference voltage terminal V.sub.R and a ground potential terminal GND. The output terminals 20 to 27 of the voltage divider 10 are connected to reference voltage input terminals of respective comparators 30 to 37. The outputs of the comparators 30 to 37 are coupled to respective logic gates 40 to 47 which constitute a position detection logic circuit 50. The outputs of the position detection logic circuit 50 are coupled to an encoder circuit 51 which has digital output terminals 152 to 154.
In operation, an analog input voltage V.sub.s is applied simultaneously to the comparators 30 to 37 which are referenced by different voltages. At this time, comparators, in which the analog input voltage exceeds the reference voltage, provide a low level output, i.e., a "0" output (after inversion). On the other hand, comparators, in which the analog input voltage V.sub.s is below the reference voltage, provide a high level output. i.e., a "1" output (after inversion). In other words, with respect to values of the analog input voltage V.sub.s the comparators 30 to 37 are classed into two groups, namely one consisting of comparators providing the "0" output and the other consisting of comparators providing the "1" output. The position detection logic circuit 50 detects the boundary between the "0" output comparator group and "1" output comparator group. Thus, of the logic gates 40 to 47, one corresponding to the boundary position provides a "1" output. The output of the position detection logic circuit 50 is encoded in the encoder 51 to obtain a 3-bit digital output. In many cases, a read only memory (ROM) type encoder as shown in FIG. 2a is used as the encoder 51, and its output is a binary code as shown in FIG. 2b. In FIG. 2a, designated at 140 to 147 are selection input terminals, and at 152 to 154 are digital output terminals. The encoder 51 has a control terminal pattern corresponding to the binary code format and respective control terminals 51a are connected to corresponding one of the selection input terminals 140 to 147. When an operation signal VGG is applied, each of the digital output terminals 152 to 154 receive either direct power source voltage V.sub.cc (logic "1") or ground potential (logic "0") responsive to turn-on of the associated control terminal. With this encoder 51 using a binary code, however, an entirely different code is produced if two selection input terminals are simultaneously selected. For example, if it happens that the comparison between analog input voltage V.sub.s and reference voltage in the comparator 33, for instance, produces too small a difference to cause perfect inversion of the comparator output so that the output is at an intermediate level "X" between "0" and "1", the intermediate level is supplied to inputs of the gates 42 to 44 in the position detection logic circuit 50. At this time, the output of the gate 42 is "0" since the output of the comparator 32 is completely "0".
Also, since the outputs of the comparators 34 to 37 are all "1", the outputs of the gates 43 and 44 are determined by the output level "X" of the comparator 33. At this time, if the input threshold value V.sub.TP of the voltage on the non-inverted input terminal of the gate 43 is somewhat lower than the rated value while the input threshold value V.sub.TN of the voltage on the inverted input terminal of the gate 44 is somewhat higher, the non-inverted input to the gate 43 is "1" while the inverted input to the gate 44 is "0", so that both the gates 43 and 44 provide a "1" output. In consequence, the selection input terminals 143 and 144 of the encoder 51 are simultaneously selected. That is, the binary code "011" corresponding to the selection input terminal 143 and the binary code "100" corresponding to the selection input terminal 144 overlap on each other, so that an entirely different binary code of "000" appears at the output terminals of the encoder 51. This phenomenon is a fatal defect to the A/D converter. More particularly, instead of a normal sequence of codes such as "011".fwdarw."100", there occurs an abnormal sequence of codes such as "011".fwdarw."000".fwdarw."100", that is, monotonicity of the A/D converter is impaired. In order to eliminate the occurrence of such a situation, it is necessary to prevent the comparator output from assuming an intermediate level at any time. To this end, precision and gain of the comparator must be increased.
However, as mentioned earlier, the parallel comparison type A/D converter requires 2.sup.N comparators where N is the number of bits of the A/D converter output. That is, if it is intended to increase the precision of conversion by increasing the bit number N, an increased number of comparators must be used. The fact that these many comparators require high precision of comparison and high gain necessarily leads to a complicated and large-scale circuit construction. Such a parallel comparison type A/D converter does not permit easy design for its implementation as a monolithic IC. Besides, an increased chip area is inevitable.